An Optimized Architecture for Binary Huff Curves With Improved Security

In order to compute the elliptic curve point addition and doubling, unified law provides better protection against side channel attacks. One of models, providing addition, is Binary Huff Curves (BHC). Recently, a new method for BHC with improved security attacks, has been proposed. Therefore, an optimized hardware architecture in terms higher clock frequency throughput required. Consequently, this article three major contributions: The first contribution modify from implementation view, resulting 31% decrease memory requirements. second analysis context pipelining. regard, proposes instruction scheduling policy 2-stage pipelined which 36% reduction number required cycles, 14.3% improvement frequency, 53.2% computation time 54.5% throughput/area. Finally, third propose 4-stage architecture. proposed additional 19% 10% increase throughput, as compared